An efficient parallel critical path tracing for path delay fault simulation

صباغیان بیدگلی, حسین; احترام, احمد; قسوری, حسین; دلشاد, مجید; حسابی, شاهین

doi:10.22052/scj.2022.246420.1068

An efficient parallel critical path tracing for path delay fault simulation

نوع مقاله : مقاله پژوهشی کوتاه

نویسندگان

¹ گروه مهندسی کامپیوتر، دانشگاه کاشان، کاشان، ایران.

² گروه مهندسی برق، واحد کاشان، دانشگاه آزاد اسلامی، کاشان، ایران.

³ گروه مهندسی برق، واحد اصفهان (خوراسگان)، دانشگاه آزاد اسلامی، اصفهان، ایران.

⁴ گروه مهندسی کامپیوتر، دانشگاه صنعتی شریف، تهران، ایران.

10.22052/scj.2022.246420.1068

چکیده

Delay fault simulation is the most general method that is used to assess the quality of generated test sets. Path delay fault is one of the most frequently used delay fault models. Path delay fault simulation is a time-consuming operation, especially for today's complex digital circuits. In this work, a novel critical path tracing algorithm is proposed for parallel path delay fault simulation. The obtained outcomes denote 489 times average speedup compared with the traditional path tracing, as well as 186 times average speed-up in comparison with the latest reported results of previous studies.

کلیدواژه‌ها

عنوان مقاله [English]

An efficient parallel critical path tracing for path delay fault simulation

نویسندگان [English]

Hossein Sabaghian-Bidgoli ¹
Ahmad Ehteram ²
Hossein Ghasvari ²
Majid Delshad ³
Shaahin Hessabi ⁴

¹ Department of Computer Engineering, University of Kashan, Kashan, Iran.

² Department of Electrical Engineering, Kashan Branch, Islamic Azad University, Kashan, Iran.

³ Department of Electrical Engineering, Isfahan (Khorasgan) Branch, Islamic Azad University, Isfahan, Iran.

⁴ Department of Computer Engineering, Sharif University of Technology, Tehran, Iran.

چکیده [English]

کلیدواژه‌ها [English]

Path delay fault
Fault simulation
Critical path tracing
Robust path
Non-robust path

مراجع

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