An Efficient Parallel Critical Path Tracing for Path Delay Fault Simulation

مقالات آماده انتشار

نوع مقاله : مقاله پژوهشی

نویسندگان

1 گروه مهندسی کامپیوتر، دانشکده مهندسی برق و کامپیوتر، دانشگاه کاشان

2 دانشکده مهندسی برق و کامپیوتر، گروه مهندسی برق، واحد کاشان، دانشگاه آزاد اسلامی، کاشان، ایران.

3 گروه مهندسی برق، واحد کاشان، دانشگاه آزاد اسلامی، کاشان، ایران

4 گروه مهندسی برق، واحد اصفهان (خوراسگان)، دانشگاه آزاد اسلامی، اصفهان، ایران

5 دانشکده مهندسی کامپیوتر، دانشگاه صنعتی شریف، تهران، ایران

چکیده

Delay fault simulation is the most general method that is used to assess the quality of generated test sets. Path delay fault is one of the most frequently used delay fault models. Path delay fault simulation is a time-consuming operation, especially for today’s complex digital circuits. In this work, a novel critical path tracing algorithm is proposed for parallel path delay fault simulation. The obtained outcomes denote 489 times average speedup compared with the traditional path tracing, as well as 186 times average speed-up in comparison with the latest reported results of previous studies.

کلیدواژه‌ها

عنوان مقاله [English]

An Efficient Parallel Critical Path Tracing for Path Delay Fault Simulation

نویسندگان [English]

  • Hossein Sabaghian-Bidgoli 1
  • Ahmad Ehteram 2
  • Hossein Ghasvari 3
  • Majid Delshad 4
  • Shaahin Hessabi 5
1 Department of Computer Engineering, Faculty of Electrical and Computer Engineering, University of Kashan, Kashan, Iran
2 Faculty of Electrical and Computer Engineering, Department of Electrical Engineering, Kashan Branch, Islamic Azad university
3 Faculty of Electrical and Computer Engineering, Department of Electrical Engineering, Kashan Branch, Islamic Azad university
4 .Faculty of Engineering,, Department of Electrical Engineering, Isfahan Branch, (Khorasgan), Islamic Azad university
5 Department of Computer Engineering, Sharif University of Technology
چکیده [English]

Delay fault simulation is the most general method that is used to assess the quality of generated test sets. Path delay fault is one of the most frequently used delay fault models. Path delay fault simulation is a time-consuming operation, especially for today’s complex digital circuits. In this work, a novel critical path tracing algorithm is proposed for parallel path delay fault simulation. The obtained outcomes denote 489 times average speedup compared with the traditional path tracing, as well as 186 times average speed-up in comparison with the latest reported results of previous studies.

کلیدواژه‌ها [English]

  • Path delay fault
  • Fault simulation
  • Critical Path Tracing
  • Robust path
  • Non-robust path
محاسبات نرم

مقالات آماده انتشار، پذیرفته شده
انتشار آنلاین از تاریخ 09 مهر 1401

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سابقه مقاله

  • تاریخ دریافت: 06 خرداد 1401
  • تاریخ بازنگری: 19 خرداد 1401
  • تاریخ پذیرش: 09 مرداد 1401

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