روش بهینۀ تصحیح سریع دیجیتالی خطا در مبدل آنالوگ به دیجیتال خط لوله با الگوریتم DLMS

[1] A. Delic-Ibukic and D. M. Hummels, "Continuous digital calibration of pipeline A/D converters," IEEE Transactions on Instrumentation and Measurement, vol. 55, pp. 1175-1185, 2006. [2] E. B. Blecker, T. M. McDonald, O. E. Erdogan, P. J. Hurst, and S. H. Lewis, "Digital background calibration of an algorithmic analog-to-digital converter using a simplified queue," IEEE Journal of Solid-State Circuits, vol. 38, pp. 1059-1062, 2003. [3] J. McNeill, M. C. Coln, and B. J. Larivee, "" Split ADC" architecture for deterministic digital background calibration of a 16-bit 1-MS/s ADC," IEEE Journal of Solid-State Circuits, vol. 40, pp. 2437-2445, 2005. [4] I. Ahmed and D. Johns, "An 11-bit 45 MS/s pipelined ADC with rapid calibration of DAC errors in a multibit pipeline stage," IEEE Journal of Solid-State Circuits, vol. 43, pp. 1626-1637, 2008. [5] Y. Chiu, C. W. Tsang, B. Nikolić, and P. R. Gray, "Least mean square adaptive digital background calibration of pipelined analog-to-digital converters," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 51, pp. 38-46, 2004. [6] A. Tahmasebi, A. Kamali, Z. K. Kanani, and J. Sobhi, "A simple background interstage gain calibration technique for pipeline ADCs," International Conference on Signal Acquisition and Processing. ICSAP 2009, pp. 221-224, 2009. [7] Y.-S. Shu and B.-S. Song, "A 15-bit linear 20-MS/s pipelined ADC digitally calibrated with signal-dependent dithering," IEEE Journal of Solid-State Circuits, vol. 43, pp. 342-350, 2008. [8] E. Siragusa and I. Galton, "A digitally enhanced 1.8-V 15-bit 40-MSample/s CMOS pipelined ADC," IEEE Journal of Solid-State Circuits, vol. 39, pp. 2126-2138, 2004. [9] B. D. Sahoo and B. Razavi, "A 12-bit 200-mhz cmos adc," IEEE Journal of Solid-State Circuits, vol. 44, pp. 2366-2380, 2009. [10] A. Verma and B. Razavi, "A 10b 500-MHz 55 mW CMOS ADC," IEEE Journal of Solid-State Circuits, vol. 44, no. 11, pp. 3039-3050, Nov. 2009. [11] B. D. Sahoo and B. Razavi, "A 10-b 1-GHz 33-mW CMOS ADC," IEEE Journal of Solid-State Circuits, vol. 48, pp. 1442-1452, 2013. [12] B. Sahoo, "An overview of digital calibration techniques for pipelined ADCs," 2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 1061-1064, 2014. [13] H. Meng and J. Sun, "A 1.2 v 10bit 83msps pipeline adc in 130nm cmos," in 2009 Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PrimeAsia), pp. 177-180, 2009. [14] B. Razavi, Principles of data conversion system design: IEEE press, 1995. [15] S.-h. Chiang, "High-Speed, Low-Power Analog-to-Digital Converters," Ph.D. dissertation, University of California, Los Angeles, 2013. [16] J. M. Ingino and B. Wooley, "A continuously calibrated 12-b, 10-MS/s, 3.3-VA/D converter," IEEE Journal of Solid-State Circuits, vol. 33, pp. 1920-1931, 1998. [17] L. Hae-Seung, "A 12-b 600 ks/s digitally self-calibrated pipelined algorithmic ADC," IEEE Journal of Solid-State Circuits, vol. 29, pp. 509-515, 1994. [18] B. Razavi, Design of Analog CMOS Integrated Circuits. New York: McGraw-Hill, 2001. [19] B. Widrow and S. D. Stearns, Adaptive Signal Processing. Englewood Cliffs, NJ, USA: Prentice-Hall, 1985. [20] B. Murmann and B. E. Boser, "A 12-bit 75-MS/s pipelined ADC using open-loop residue amplification," IEEE Journal of Solid-State Circuits, vol. 38, no. 12, pp. 2040–2050, Dec. 2003. [21] N. T. Abou-El-Kheir, M. E. Khedr, and M. Abbas, "A fast power efficient equalization-based digital background calibration technique for pipelined ADC," 2014 Proceedings of the 21st International Conference in Mixed Design of Integrated Circuits & Systems (MIXDES), pp. 108-112, 2014. [22] A. Tahmasebi, A. Kamali, Z. K. Kanani, and J. Sobhi, "A simple background interstage gain calibration technique for pipeline ADCs," International Conference on Signal Acquisition and Processing. ICSAP 2009, pp. 221-224, 2009. [23] X. Wang, P. J. Hurst, and S. H. Lewis, "A 12-bit 20-Msample/s pipelined analog-to-digital converter with nested digital background calibration," IEEE Journal of Solid-State Circuits, vol. 39, no. 11, pp. 1799–1808, Nov. 2004. [24] O. E. Erdoğan, P. J. Hurst, and S. H. Lewis, "A 12-b digital-background-calibrated algorithmic ADC with-90-dB THD," IEEE Journal of Solid-State Circuits, vol. 34, pp. 1812-1820, 1999. [25] E. B. Blecker, T. M. McDonald, O. E. Erdogan, P. J. Hurst, and S. H. Lewis, "Digital background calibration of an algorithmic analog-to-digital converter using a simplified queue," IEEE Journal of Solid-State Circuits, vol. 38, pp. 1059-1062, 2003. [26] C. R. Grace, P. J. Hurst, and S. H. Lewis, "A 12-bit 80-Msample/s pipelined ADC with bootstrapped digital calibration," IEEE Journal of Solid-State Circuits, vol. 40, no. 5, pp. 1038–1046, May 2005. [27] A. Panigada and I. Galton, "A 130 mW 100 MS/s pipelined ADC with 69 dB SNDR enabled by digital harmonic distortion correction," IEEE Journal of Solid-State Circuits, vol. 44, pp. 3314-3328, 2009.