In the electronics industry, scaling and optimization is final goal. But, according to ITRS predictions, silicon as basic material for semiconductors, is facing physical limitation and approaching the end of the path. Therefore, researchers are looking for the silicon replacement. Until now, carbon and its allotrope, graphene, look to be viable candidates. Among different circuits, IO block is a needed ingredient for electronic systems and needs to be re-designed and optimized. In this paper, goal is feasibility analysis and design of IO blocks using graphene field effect transistors. Using these transistors, each ingredient is designed, simulated and analyzed using the HSPICE tool. Then, these ingredients are combined together and the graphene-based IO block is implemented. Similar to graphene IO, silicon- based IO block is also designed and results are compared. It indicated that propagation delay is 299.9ps with 10% edge roughness, which is 32% faster compared to silicon counterpart.
[1] L. Wilson, "International technology roadmap for semiconductors (ITRS)," Semiconductor Industry Association, 2013.
[2] Y.-M. Lin, A. Valdes-Garcia, S.-J. Han, D. B. Farmer, I. Meric, Y. Sun, et al., "Wafer-scale graphene integrated circuit," Science, vol. 332, pp. 1294-1297, 2011.
[3] H. Wang, A. Hsu, J. Wu, J. Kong, and T. Palacios, "Graphene-based ambipolar RF mixers," IEEE Electron Device Letters, vol. 31, pp. 906-908, 2010.
[4] S. A. S. Kashani, H. K. Alidash, and S. Miryala, "Design and characterization of graphene nano-ribbon based D-flip-flop," Journal of Nanoelectronics and Optoelectronics, vol. 12, pp. 580-591, 2017.
[5] S. A. S. Kashani, H. K. Alidash, and S. Miryala, "Schottky-barrier graphene nanoribbon field-effect transistors-based field-programmable gate array's configurable logic block and routing switch," IET Circuits, Devices & Systems, vol. 11, pp. 549-558, 2017.
[6] J. M. Rabaey, A. P. Chandrakasan, and B. Nikolić, Digital Integrated Circuits, 2/e: Prentice hall, 2003.
[7] N. H. Weste and D. Harris, CMOS VLSI design: a circuits and systems perspective: Pearson Education India, 2015.
[8] S. G. Noyce, J. L. Doherty, Z. Cheng, H. Han, S. Bowen, and A. D. Franklin, "Electronic Stability of Carbon Nanotube Transistors Under Long-term Bias Stress," Nano letters, 2019.
[9] M. Cao, C. Han, X. Wang, M. Zhang, Y. Zhang, J. Shu, et al., "Graphene nanohybrids: excellent electromagnetic properties for the absorbing and shielding of electromagnetic waves," Journal of Materials Chemistry C, vol. 6, pp. 4586-4602, 2018.
[10] A. Geim, "Graphene prehistory," Physica Scripta, vol. 2012, p. 014003, 2012.
[11] M. C. Lemme, T. J. Echtermeyer, M. Baus, and H. Kurz, "A graphene field-effect device," IEEE Electron Device Letters, vol. 28, pp. 282-284, 2007.
[12] R. Cheng, J. Bai, L. Liao, H. Zhou, Y. Chen, L. Liu, et al., "High-frequency self-aligned graphene transistors with transferred gate stacks," Proceedings of the National Academy of Sciences, vol. 109, pp. 11588-11592, 2012.
[13] X. Wang, Y. Ouyang, X. Li, H. Wang, J. Guo, and H. Dai, "Room-temperature all-semiconducting sub-10-nm graphene nanoribbon field-effect transistors," Physical review letters, vol. 100, p. 206803, 2008.
[14] J. Wang, F. Ma, and M. Sun, "Graphene, hexagonal boron nitride, and their heterostructures: properties and applications," RSC Advances, vol. 7, pp. 16801-16822, 2017.
[15] M. Gholipour, Y.-Y. Chen, A. Sangai, and D. Chen, "Highly accurate SPICE-compatible modeling for single-and double-gate GNRFETs with studies on technology scaling," in Proceedings of the conference on Design, Automation & Test in Europe, 2014, p. 120.
[16] PTM. Predictive Technology Model [Online].
Shirvani Filabadi, H., & Karimiyan, H. (2021). Design and Optimization of Input-Output Block using Graphene Nano-ribbon Transistors. Soft Computing Journal, 7(2), 24-35.
MLA
Hadi Shirvani Filabadi; Hossein Karimiyan. "Design and Optimization of Input-Output Block using Graphene Nano-ribbon Transistors", Soft Computing Journal, 7, 2, 2021, 24-35.
HARVARD
Shirvani Filabadi, H., Karimiyan, H. (2021). 'Design and Optimization of Input-Output Block using Graphene Nano-ribbon Transistors', Soft Computing Journal, 7(2), pp. 24-35.
VANCOUVER
Shirvani Filabadi, H., Karimiyan, H. Design and Optimization of Input-Output Block using Graphene Nano-ribbon Transistors. Soft Computing Journal, 2021; 7(2): 24-35.
)
