Volume 4, Issue 1 (3-2016)                   SCJ 2016, 4(1): 30-41 | Back to browse issues page

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Low-Power Soft-Error Hardened Static Latch. SCJ. 2016; 4 (1) :30-41
URL: http://scj.kashanu.ac.ir/article-1-184-en.html
Abstract:   (1066 Views)

The importance of the reliability in circuits, especially the effect of cosmic ray and the faults caused by the particles hit are becoming increasingly important as the CMOS technology progresses from sub-micrometer to nanometer scale. In this paper a static latch presented which is resistant to soft error caused by energetic particles hit to the surface of the chip and suitable for high reliability applications. The hardening method is based on deploying multiple feedback paths in the opaque mode of the latch. The HSPICE post-layout simulation results in 65nm CMOS technology reveal that the proposed structures besides to single and multiple node resilience and reduced error-rate, introduce more than 13 percent reduction in delay and power consumption compared to similar structures.

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Type of Study: Applicable | Subject: Special
Received: 2014/10/9 | Accepted: 2015/08/14 | Published: 2016/04/13

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